Messages in this thread | | | Date | Thu, 18 Jul 2013 10:41:29 +0200 | From | Peter Zijlstra <> | Subject | Re: [PATCH] perf, x86: Add Silvermont (22nm Atom) support |
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On Thu, Jul 18, 2013 at 01:36:07PM +0800, Yan, Zheng wrote:
> @@ -1305,7 +1452,7 @@ static void intel_fixup_er(struct perf_event *event, int idx) > event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0; > } else if (idx == EXTRA_REG_RSP_1) { > event->hw.config &= ~INTEL_ARCH_EVENT_MASK; > - event->hw.config |= 0x01bb; > + event->hw.config |= x86_pmu.extra_regs[1].event; > event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1; > } > }
When you do the split up, please make this consistent and use x86_pmu.extra_regs[0].event as well.
Also, ideally we'd use EXTRA_REG_RSP_[01] instead of the 0 and 1.
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