Messages in this thread | | | Date | Tue, 16 Jul 2013 16:59:08 -0700 | Subject | Re: [PATCH v5] x86: make sure IDT is page aligned | From | Yinghai Lu <> |
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On Tue, Jul 16, 2013 at 4:43 PM, H. Peter Anvin <hpa@zytor.com> wrote: > On 07/16/2013 04:39 PM, Yinghai Lu wrote: >> >> ok. so the old code is just for optimization to keep it cacheline aligned? >> > > To the best of my knowledge. I guess I should look through the git log > to make sure it isn't some old erratum fix. > looks like before commit e57113bc1ff591005ec0b0fb4885d97c01de73d8 Author: Jan Beulich <jbeulich@novell.com> Date: Sat Mar 25 16:30:01 2006 +0100
[PATCH] x86_64: miscellaneous cleanup
- adjust limits of GDT/IDT pseudo-descriptors (some were off by one) - move empty_zero_page into .bss.page_aligned - move cpu_gdt_table into .data.page_aligned - move idt_table into .bss - align inital_code and init_rsp - eliminate pointless (re-)declaration of idt_table in traps.c
it is PAGE aligned as it is after gdt page, after the commit, it is cacheline aligned.
@@ -378,9 +378,12 @@ gdt_end: /* zero the remaining page */ .fill PAGE_SIZE / 8 - GDT_ENTRIES,8,0
-ENTRY(idt_table) - .rept 256 - .quad 0 - .quad 0 - .endr + .section .bss, "aw", @nobits + .align L1_CACHE_BYTES +ENTRY(idt_table) + .skip 256 * 16
+ .section .bss.page_aligned, "aw", @nobits + .align PAGE_SIZE +ENTRY(empty_zero_page) + .skip PAGE_SIZE
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