Messages in this thread | | | From | Grant Likely <> | Date | Mon, 3 Jun 2013 10:51:06 +0100 | Subject | Re: [PATCH V3] irqchip: Add TB10x interrupt controller driver |
| |
On Mon, Jun 3, 2013 at 5:05 AM, Vineet Gupta <Vineet.Gupta1@synopsys.com> wrote: > On 06/01/2013 03:48 AM, Grant Likely wrote: >> If I were working on this system I'd drop the >> snps,arc700-intc node entirely and have a single abilis,tb10x-intc that >> encapsulated the properties of both (you would of course want to share >> handler functions for the 'normal' inputs without the custom features). >> That would eliminate the goofyness of listing 27 separate interrupts in >> the abilis,tb10x-ictl interrupts property. > > But how is this different from other systems with a primary in-core intc and a > cascaded external intc. How do they do it. I guess I need to read up more on this.
Usually cascaded irq controllers have multiple irqs multiplexed onto a single irq on the parent controller. It's the 1:1 situation that makes this controller odd.
g,
| |