Messages in this thread | | | From | Mike Turquette <> | Subject | Re: [PATCH 3/3] clk: tegra: T114: add DFLL DVCO reset control | Date | Sat, 15 Jun 2013 21:22:56 -0700 |
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Quoting Paul Walmsley (2013-06-11 02:47:13) > On Tue, 11 Jun 2013, Prashant Gaikwad wrote: > > > Why not implement these APIs in DFLL clock driver itself and pass RST address > > register to driver? > > The DFLL DVCO reset registers are CAR registers, not DFLL registers. > Functions that operate on registers in one IP block shouldn't be located > in another IP block's driver.
Paul & Co.,
These patches appear fine to me but I did not see any Acks, nor could I tell if a v2 was necessary based on the comments. Will there be another version? If not an Acked-by or Reviewed-by would be cool.
Regards, Mike
> > > - Paul
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