lkml.org 
[lkml]   [2013]   [Jun]   [16]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
From
SubjectRe: [PATCH 3/3] clk: tegra: T114: add DFLL DVCO reset control
Date
Quoting Paul Walmsley (2013-06-11 02:47:13)
> On Tue, 11 Jun 2013, Prashant Gaikwad wrote:
>
> > Why not implement these APIs in DFLL clock driver itself and pass RST address
> > register to driver?
>
> The DFLL DVCO reset registers are CAR registers, not DFLL registers.
> Functions that operate on registers in one IP block shouldn't be located
> in another IP block's driver.

Paul & Co.,

These patches appear fine to me but I did not see any Acks, nor could I
tell if a v2 was necessary based on the comments. Will there be another
version? If not an Acked-by or Reviewed-by would be cool.

Regards,
Mike

>
>
> - Paul


\
 
 \ /
  Last update: 2013-06-16 06:41    [W:0.046 / U:0.704 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site