Messages in this thread | | | Date | Mon, 10 Jun 2013 14:48:48 -0700 | From | Sukadev Bhattiprolu <> | Subject | Re: [PATCH 1/2] perf/Power7: Save dcache_src fields in sample record. |
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Anshuman Khandual [khandual@linux.vnet.ibm.com] wrote: | > The former approach seems less confusing and this patch uses that approach. | > | | Yeah, the former approach is simpler and makes sense.
Ok. Seems to make sense at least on Power.
<snip>
| > + * We use the table, dcache_src_map, to map this value 1 to PERF_MEM_LVL_L3, | > + * the arch-neutral representation of the L3 cache. | > + * | > + * Similarly, in case of marked data TLB miss, bits 14..17 of the MMCRA | > + * indicate the load source of a marked DTLB entry. dtlb_src_map[] gives | > + * the mapping to the arch-neutral values of the TLB source. | | | Where did you define dtlb_src_map[] ?
Ah, the comment belongs in another patch that I am working on. That patch maps the PERF_MEM_TLB* flags to Power7.
Thanks for the comments.
Sukadev
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