Messages in this thread | | | Date | Wed, 1 May 2013 23:53:58 -0700 | From | Bin Gao <> | Subject | Re: x86/pci/mrst: force all pci config toward 0:0:0, 0:2:0 and 0:3:0 to type 1 |
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On Wed, May 01, 2013 at 11:17:10AM -0600, Bjorn Helgaas wrote: > Is there any possibility of multi-function devices at bus 0, device 0, 2, or 3? > > What about bridges -- can any of these be a bridge? > > If either of those could happen, these checks could be too specific. 0:2:0 and 0:3:0 are the only 2 devices behind the bridge 0:0:0. These devices don't implement pcie capability list in legacy config space so no offset above 255 would be triggered. The fixed bar pcie capability located at 0x100 is for pci-shimed device only, not for 0, 2 and 3. But current implementation applies it to 0, 2 and 3 as well. This is what the patch is going to address.
> > Is there a doc that identifies these cases where config mechanism #1 > should be used instead of MMCONFIG? Unfortunately no doc identifies this. But since FW doesn't provide pci shim for device 0, 2 and 3, and these 3 real pci devices have only 256 bytes legacy pci config space so they can only be accessed by type 1.
> > Bjorn >
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