Messages in this thread | | | From | Kukjin Kim <> | Subject | RE: [PATCH] clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3} | Date | Mon, 08 Apr 2013 16:22:58 +0900 |
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Mike Turquette wrote: > > Quoting Tushar Behera (2013-04-02 01:20:40) > > In legacy setup, sclk_mmc{0,1,2,3} used PRE_RATIO bit-field (8-bit wide) > > instead of RATIO bit-field (4-bit wide) for dividing clock rate. > > > > With current common clock setup, we are using RATIO bit-field which > > is creating FIFO read errors while accessing eMMC. Changing over to > > use PRE_RATIO bit-field fixes this issue. > > > > dwmmc_exynos 12200000.dwmmc0: data FIFO error (status=00008020) > > mmcblk0: error -5 transferring data, sector 1, nr 7, cmd response 0x900, > card status 0x0 > > end_request: I/O error, dev mmcblk0, sector 1 > > > > Signed-off-by: Tushar Behera <tushar.behera@linaro.org> > > CC: Thomas Abraham <thomas.abraham@linaro.org> > > I guess this will be applied through the samsung tree, so: > > Acked-by: Mike Turquette <mturquette@linaro.org> > Thanks, applied.
- Kukjin
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