Messages in this thread Patch in this message | | | Subject | [PATCH 2/2] PM / devfreq: exynos4_bus: Fix table entry size for exynos4x12_clkdiv_dmc1 | From | Axel Lin <> | Date | Wed, 20 Mar 2013 16:15:34 +0800 |
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exynos4x12_clkdiv_dmc1 contains { G2DACP, DIVC2C, DIVC2C_ACLK }, thus set the size to 3 rather than 6.
Signed-off-by: Axel Lin <axel.lin@ingics.com> --- drivers/devfreq/exynos4_bus.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/devfreq/exynos4_bus.c b/drivers/devfreq/exynos4_bus.c index 45d00d1..1deee09 100644 --- a/drivers/devfreq/exynos4_bus.c +++ b/drivers/devfreq/exynos4_bus.c @@ -235,7 +235,7 @@ static const unsigned int exynos4x12_clkdiv_dmc0[][6] = { /* DMC L4: 100MHz */ {7, 1, 1, 7, 1, 1}, }; -static const unsigned int exynos4x12_clkdiv_dmc1[][6] = { +static const unsigned int exynos4x12_clkdiv_dmc1[][3] = { /* * Clock divider value for following * { G2DACP, DIVC2C, DIVC2C_ACLK } -- 1.7.9.5
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