Messages in this thread Patch in this message | | | From | Zhao Chenhui <> | Subject | [PATCH] mpic: fix Destination Registers init problem | Date | Thu, 7 Feb 2013 16:07:00 +0800 |
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The Freescale implementation of the MPIC only allows a single CPU destination for non-IPI interrupts. Test the flag MPIC_SINGLE_DEST_CPU to check if the Destination registers should be set.
This prevents more than one bit is set at secondary processors initilizing time if the flag MPIC_SINGLE_DEST_CPU is set.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> --- arch/powerpc/sysdev/mpic.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index 9c6e535..cc537f8 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c @@ -1675,7 +1675,7 @@ void mpic_setup_this_cpu(void) * it differently, then we should make sure we also change the default * values of irq_desc[].affinity in irq.c. */ - if (distribute_irqs) { + if (distribute_irqs && !(mpic->flags & MPIC_SINGLE_DEST_CPU)) { for (i = 0; i < mpic->num_sources ; i++) mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk); -- 1.7.1
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