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SubjectRe: [PATCH] clk: tegra: initialise parent of uart clocks
On 02/06/2013 03:47 AM, Laxman Dewangan wrote:
> Initialise the parent of UARTs to PLLP


> and disabling clock by default.

Hmm. Only the clocks initialized by the new entries you added are marked
disabled (or rather, not actively enabled; if they're enabled already,
they won't be disabled). We should treat all UARTs equally. Historically
we've needed to enable the serial clocks forcibly since the regular
serial driver didn't call clk_get() or clk_prepare_enable() on any
clocks, but I notice that it does now, since sometime in kernel 3.8. As
such, I think you can modify all the UART entries in these tables to
have the enable/state field set to false (0). Can you try that and check
that it works for the serial console ports? Thanks.

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