Messages in this thread |  | | Subject | Re: [PATCH] drivers/block/xsysace - replace in(out)_8/in(out)_be16/in(out)_le16 with generic iowrite(read)8/16(be) | From | Benjamin Herrenschmidt <> | Date | Wed, 06 Feb 2013 08:01:33 +1100 |
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On Tue, 2013-02-05 at 16:12 +0100, Arnd Bergmann wrote: > Ok. In this case, I would recommend making the default for this driver > little-endian, and adding a quirk for broken hardware bridges like the > one you cited to have a mixed-endian mode if configured so at compile > time. > > It seems that on all normal platforms, this device should behave as > little-endian, while the Xilinx bridge can be either big-endian > or little-endian, depending on whether it is used in 8-bit or 16-bit > mode, so if we are using this, it cannot be known at compile time.
Why ? 8-bit devices shouldn't need anything special. 16-bit should be wired properly to not need anything special either. Why would we bother supporting a bad wiring ? Let them feel the pain, with luck it will provide incentive for them to fix it.
Ben.
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