Messages in this thread | | | Date | Wed, 13 Feb 2013 10:10:22 +0100 | From | Ingo Molnar <> | Subject | Re: [PATCH 5/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset |
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* Andi Kleen <andi@firstfloor.org> wrote:
> On Tue, Feb 12, 2013 at 09:43:46AM +0100, Ingo Molnar wrote: > > Was this stress-tested on all affected main CPU types, or only > > on Haswell? > > I tested it on Haswell and Ivy Bridge. I can also try Westmere > and a Saltwell(Atom), but for the majority of other family 6 > systems I'll need to rely on the community.
The systems you tested should be OK.
> White listing is somewhat difficult because it affects the > architectural mode too.
Yeah, I'd rather avoid that.
> I don't really expect problems from this change, we should > probably have always done it like this.
I expect potential problems: the ordering of the operations in the NMI handler was always very fragile, resulting in hard to debug hangs - which sometimes needed hours long very intense PMU stress-testing to trigger.
That is why I asked how heavily you've tested this. Once the series passes review I'll keep this patch last to make it easy to revert/zap if it causes problems.
Thanks,
Ingo
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