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Subject[PATCH 2/7] dt-bindings: Add property calxeda,pll-max-hz for Calxeda clocks
From: Rob Herring <>

Newer versions of PLL h/w have different frequency ranges for the PLLs,
but otherwise have the same programming model. Add an optional property
"calxeda,pll-max-hz" for Calxeda PLL clocks to handle this difference.

Signed-off-by: Rob Herring <>
Cc: Mike Turquette <>
Cc: Pawel Moll <>
Cc: Mark Rutland <>
Cc: Ian Campbell <>
Documentation/devicetree/bindings/clock/calxeda.txt | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/calxeda.txt b/Documentation/devicetree/bindings/clock/calxeda.txt
index 7ebc89c..9ee1b64 100644
--- a/Documentation/devicetree/bindings/clock/calxeda.txt
+++ b/Documentation/devicetree/bindings/clock/calxeda.txt
@@ -1,4 +1,4 @@
-Device Tree Clock bindings for Calxeda highbank platform
+Device Tree Clock bindings for Calxeda platforms

This binding uses the common clock binding[1].

@@ -15,3 +15,8 @@ Required properties:
- clocks : shall be the input parent clock phandle for the clock. This is
either an oscillator or a pll output.
- #clock-cells : from common clock binding; shall be set to 0.
+Optional properties:
+- calxeda,pll-max-hz : The maximum output frequency of the PLL in Hz. The
+ default is 2.133GHz if not present. This is only present for
+ "calxeda,hb-pll-clock" nodes.

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