Messages in this thread | | | From | Bartlomiej Zolnierkiewicz <> | Subject | Re: [PATCH 1/3 v8] thermal: samsung: add intclr_fall_shift bit in exynos_tmu_register struct | Date | Thu, 07 Nov 2013 11:48:42 +0100 |
| |
Hi,
On Thursday, November 07, 2013 11:22:42 AM Naveen Krishna Chatradhi wrote: > On Exynos5250, the FALL interrupt related en, status and clear bits are > available at an offset of > 16 in INTEN, INTSTAT registers and at an offset of > 12 in INTCLEAR register. > > On Exynos5420, the FALL interrupt related en, status and clear bits are > available at an offset of > 16 in INTEN, INTSTAT and INTCLEAR registers. > > On Exynos5440, > the FALL_IRQEN bits are at an offset of 4 > and the RISE_IRQEN bits are at an offset of 0 > > This patch introduces a new bit field intclr_fall_shift to handle the > offset for exyns5250 and exynos5440 > Also removes the unused macros EXYNOS_TMU_FALL_INT_SHIFT and > EXYNOS5440_TMU_FALL_INT_SHIFT, inten_fall_shift field
Thanks for fixing this. All three patches look good to me now.
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Best regards, -- Bartlomiej Zolnierkiewicz Samsung R&D Institute Poland Samsung Electronics
| |