Messages in this thread |  | | From | Jingoo Han <> | Subject | Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver | Date | Wed, 06 Nov 2013 09:07:00 +0900 |
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On Wednesday, November 06, 2013 2:58 AM, Vivek Gautam wrote: > On Tue, Nov 5, 2013 at 5:33 PM, Jingoo Han <jg1.han@samsung.com> wrote:
[.....]
>> USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block. >> This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block >> and 2.0 block, respectively. >> >> Conclusion: >> >> 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device >> Base address: 0x1213 0000 >> >> 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST & 3.0 Device) >> Base address: 0x1210 0000 >> 2.0 block(UTMI+) & 3.0 block(PIPE3) > > And this is of course the PHY used by DWC3 controller, which works at > both High speed as well as Super Speed. > Right ?
Right.
While 3.0 block(PIPE3) can be used for Super Speed, 2.0 block(UTMI+) can be used for High speed.
Best regards, Jingoo Han
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