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    SubjectRe: [RFC] arch: Introduce new TSO memory barrier smp_tmb()
    On Tue, Nov 05, 2013 at 02:05:48PM +0000, Will Deacon wrote:
    > On Mon, Nov 04, 2013 at 08:53:44PM +0000, Paul E. McKenney wrote:
    > > On Mon, Nov 04, 2013 at 08:11:27PM +0100, Peter Zijlstra wrote:
    > > Some comments below. I believe that opcodes need to be fixed for IA64.
    > > I am unsure of the ifdefs and opcodes for arm64, but the ARM folks should
    > > be able to tell us.

    [ . . . ]

    > > > +} while (0)
    > > > +
    > > > +#define smp_load_acquire(p) \
    > > > +do { \
    > > > + typeof(p) ___p1; \
    > > > + asm volatile ("ldar %w0, [%1]" \
    > > > + : "=r" (___p1) : "r" (&p) : "memory"); \
    > > > + return ___p1; \
    >
    > Similar comments here wrt Q constraint.
    >
    > Random other question: have you considered how these accessors should behave
    > when presented with __iomem pointers?

    Should we have something to make sparse yell if not __kernel or some such?

    Thanx, Paul



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