Messages in this thread Patch in this message | | | From | Yinghai Lu <> | Subject | [PATCH v3 12/12] intel-gtt: Read 64bit for gmar_bus_addr | Date | Sat, 30 Nov 2013 14:40:38 -0800 |
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That bar could be 64bit pref mem and above 4G.
-v2: refresh to 3.13-rc1
Signed-off-by: Yinghai Lu <yinghai@kernel.org> Cc: David Airlie <airlied@linux.ie> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> --- drivers/char/agp/intel-gtt.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c index b8e2014..b929e9d 100644 --- a/drivers/char/agp/intel-gtt.c +++ b/drivers/char/agp/intel-gtt.c @@ -609,8 +609,10 @@ static bool intel_gtt_can_wc(void) static int intel_gtt_init(void) { u32 gma_addr; + u32 addr_hi = 0; u32 gtt_map_size; int ret; + int pos; ret = intel_private.driver->setup(); if (ret != 0) @@ -660,13 +662,17 @@ static int intel_gtt_init(void) } if (INTEL_GTT_GEN <= 2) - pci_read_config_dword(intel_private.pcidev, I810_GMADDR, - &gma_addr); + pos = I810_GMADDR; else - pci_read_config_dword(intel_private.pcidev, I915_GMADDR, - &gma_addr); + pos = I915_GMADDR; + + pci_read_config_dword(intel_private.pcidev, pos, &gma_addr); + + if (gma_addr & PCI_BASE_ADDRESS_MEM_TYPE_64) + pci_read_config_dword(intel_private.pcidev, pos + 4, &addr_hi); intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK); + intel_private.gma_bus_addr |= (u64)addr_hi << 32; return 0; } -- 1.8.1.4
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