Messages in this thread | | | Date | Sun, 3 Nov 2013 17:07:59 +0000 | From | Will Deacon <> | Subject | Re: perf events ring buffer memory barrier on powerpc |
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On Sun, Nov 03, 2013 at 02:40:17PM +0000, Paul E. McKenney wrote: > On Sat, Nov 02, 2013 at 10:32:39AM -0700, Paul E. McKenney wrote: > > On Fri, Nov 01, 2013 at 03:56:34PM +0100, Peter Zijlstra wrote: > > > On Wed, Oct 30, 2013 at 11:40:15PM -0700, Paul E. McKenney wrote: > > > > > Now the whole crux of the question is if we need barrier A at all, since > > > > > the STORES issued by the @buf writes are dependent on the ubuf->tail > > > > > read. > > > > > > > > The dependency you are talking about is via the "if" statement? > > > > Even C/C++11 is not required to respect control dependencies. > > > > > > > > This one is a bit annoying. The x86 TSO means that you really only > > > > need barrier(), ARM (recent ARM, anyway) and Power could use a weaker > > > > barrier, and so on -- but smp_mb() emits a full barrier. > > > > > > > > Perhaps a new smp_tmb() for TSO semantics, where reads are ordered > > > > before reads, writes before writes, and reads before writes, but not > > > > writes before reads? Another approach would be to define a per-arch > > > > barrier for this particular case. > > > > > > I suppose we can only introduce new barrier primitives if there's more > > > than 1 use-case.
Which barrier did you have in mind when you refer to `recent ARM' above? It seems to me like you'd need a combination if dmb ishld and dmb ishst, since the former doesn't order writes before writes.
Will
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