Messages in this thread Patch in this message | | | From | Jon Mason <> | Subject | [PATCH 7/9] NTB: Document HW errata | Date | Wed, 20 Nov 2013 17:21:28 -0700 |
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Add a comment describing the necessary ordering of modifications to the NTB Limit and Base registers.
Signed-off-by: Jon Mason <jon.mason@intel.com> --- drivers/ntb/ntb_hw.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/drivers/ntb/ntb_hw.c b/drivers/ntb/ntb_hw.c index fa97948..391c377 100644 --- a/drivers/ntb/ntb_hw.c +++ b/drivers/ntb/ntb_hw.c @@ -689,6 +689,12 @@ static int ntb_xeon_setup(struct ntb_device *ndev) */ writeq(ndev->mw[1].bar_sz + 0x1000, ndev->reg_base + SNB_PBAR4LMT_OFFSET); + /* HW errata on the Limit registers. They can only be + * written when the base register is 4GB aligned and + * < 32bit. This should already be the case based on the + * driver defaults, but write the Limit registers first + * just in case. + */ } else { ndev->limits.max_mw = SNB_MAX_MW; @@ -707,6 +713,12 @@ static int ntb_xeon_setup(struct ntb_device *ndev) * something silly */ writeq(0, ndev->reg_base + SNB_PBAR4LMT_OFFSET); + /* HW errata on the Limit registers. They can only be + * written when the base register is 4GB aligned and + * < 32bit. This should already be the case based on the + * driver defaults, but write the Limit registers first + * just in case. + */ } /* The Xeon errata workaround requires setting SBAR Base -- 1.7.9.5
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