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Subject[PATCH] i915: Use 120MHz LVDS SSC clock for gen5/gen6/gen7
From: Duncan Laurie <>

We had been using a DMI table workaround to select the right
frequency for devices, but this is fragile and must be updated
with every new platform.

Instead the default case when VBT is missing is changed to use
120MHz clock for LVDS SSC for these generations.

The docs for 2010-Core, SandyBridge, and IvyBridge all indicate
that the reference frequency for LVDS is 120MHz:

"2010 Core"
page 38
Reference Frequency: 120MHz for CRT and LVDS. 100MHz for the FDI.

"2011 SandyBridge"
page 33
Reference Frequency: 120MHz for CRT, HDMI, LVDS. 100MHz for the FDI.

"2012 IvyBridge"
page 27
Reference Frequency: 120 MHz for CRT, HDMI, LVDS, 100MHz for the FDI.

Signed-off-by: Duncan Laurie <>
[olof: Fixup for recent base, switched from if/else to single call]
Signed-off-by: Olof Johansson <>


This applies on top of -next, which I'm presuming is close to your
for-3.13 base right now. It'd be good to see this go in since it's needed
to boot on Chromebooks (with developer mode off), and is thus blocking
testing next/mainline on a regular basis here.



drivers/gpu/drm/i915/intel_bios.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 6dd622d733b9..e4fba39631a5 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -790,7 +790,12 @@ init_vbt_defaults(struct drm_i915_private *dev_priv)

/* Default to using SSC */
dev_priv->vbt.lvds_use_ssc = 1;
- dev_priv->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(dev, 1);
+ /*
+ * Core/SandyBridge/IvyBridge use alternative (120MHz) reference
+ * clock for LVDS.
+ */
+ dev_priv->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(dev,
+ !HAS_PCH_SPLIT(dev));
DRM_DEBUG_KMS("Set default to SSC at %dMHz\n", dev_priv->vbt.lvds_ssc_freq);

for (port = PORT_A; port < I915_MAX_PORTS; port++) {

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