Messages in this thread | | | Date | Wed, 09 Oct 2013 15:21:41 -0700 | From | "H. Peter Anvin" <> | Subject | Re: [RFC PATCH v2 0/1] FPGA subsystem core |
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On 10/09/2013 02:07 PM, Jason Gunthorpe wrote: > That is sort of backwards though, how does the driver know it should > load and start fpga progamming?
A common way is for there to be a bitstream stored in flash which presents an interface to download the data. I think some FPGAs with hard bus IP even has that built in.
Another variant -- common on USB -- is to use a simple USB interface chip like an FTDI which can be used (sometimes in conjunction with a CPLD) to (in effect) bitbang in a bitstream into the FPGA. After configuration, the programming pins are used for the USB interface.
-hpa
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