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SubjectRe: [PATCH v1 1/2] perf,x86: add Intel RAPL PMU support
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Stephane Eranian <eranian@google.com> writes:
>
>>> + goto again;
>>> +
>>> + struct rapl_pmu *pmu = __get_cpu_var(rapl_pmu);
>>> +
>>> + if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
>>> + return;
>>> +
>>> + event->hw.state = 0;
>>> +
>>> + local64_set(&event->hw.prev_count, rapl_read_counter(event));
>>> +
>>> + pmu->n_active++;
>>
>> What lock protects this add?
>>
> None. I will add one. Bu then I am wondering about if it is really
> necessary given
> that RAPL event are system-wide and this pinned to a CPU. If the call came
> from another CPU, then it IPI there, and that means that CPU is executing that
> code. Any other CPU will need IPI too, and that interrupt will be kept pending.
> Am I missing a test case here? Are IPI reentrant?

they can be if interrupts are enabled (likely here)

>
>>> +}
>>> +
>>> +static ssize_t rapl_get_attr_cpumask(struct device *dev,
>>> + struct device_attribute *attr, char *buf)
>>> +{
>>> + int n = cpulist_scnprintf(buf, PAGE_SIZE - 2, &rapl_cpu_mask);
>>
>> Check n here in case it overflowed
>>
> But isn't that what the -2 and the below \n\0 are for?

I know it's very unlikely and other stuff would break, but

Assuming you have a system with some many CPUs that they don't fit
into a page. Then the scnprintf would fail, but you would corrupt
random data because you write before the buffer.

>> Doesn't this need a lock of some form? AFAIK we can do parallel
>> CPU startup now.
>>
> Did not know about this change? But then that means all the other
> perf_event *_starting() and maybe even _*prepare() routines must also
> use locks. I can add that to RAPL.

Yes may be broken everywhere.

>>> + /* check supported CPU */
>>> + switch (boot_cpu_data.x86_model) {
>>> + case 42: /* Sandy Bridge */
>>> + case 58: /* Ivy Bridge */
>>> + case 60: /* Haswell */
>>
>> Need more model numbers for Haswell (see the main perf driver)
>>
> Don't have all the models to test...

It should be all the same.

-Andi
--
ak@linux.intel.com -- Speaking for myself only


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