lkml.org 
[lkml]   [2013]   [Oct]   [4]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH v7 3/5] ARM: tegra: split setting of CPU reset handler
    Date
    Not all Tegra devices can set the CPU reset handler in the same way.
    In particular, devices using a TrustZone secure monitor cannot set the
    reset handler directly and need to do it through a firmware operation.

    This patch separates the act of setting the reset handler from its
    preparation, so the former can be implemented in a different way.

    Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
    Reviewed-by: Tomasz Figa <t.figa@samsung.com>
    Reviewed-by: Stephen Warren <swarren@nvidia.com>
    ---
    arch/arm/mach-tegra/reset.c | 27 +++++++++++++++++----------
    1 file changed, 17 insertions(+), 10 deletions(-)

    diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
    index fd0bbf8..e282395 100644
    --- a/arch/arm/mach-tegra/reset.c
    +++ b/arch/arm/mach-tegra/reset.c
    @@ -33,26 +33,18 @@

    static bool is_enabled;

    -static void __init tegra_cpu_reset_handler_enable(void)
    +static void __init tegra_cpu_reset_handler_set(const u32 reset_address)
    {
    - void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE);
    void __iomem *evp_cpu_reset =
    IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100);
    void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE);
    u32 reg;

    - BUG_ON(is_enabled);
    - BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE);
    -
    - memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start,
    - tegra_cpu_reset_handler_size);
    -
    /*
    * NOTE: This must be the one and only write to the EVP CPU reset
    * vector in the entire system.
    */
    - writel(TEGRA_IRAM_RESET_BASE + tegra_cpu_reset_handler_offset,
    - evp_cpu_reset);
    + writel(reset_address, evp_cpu_reset);
    wmb();
    reg = readl(evp_cpu_reset);

    @@ -66,6 +58,21 @@ static void __init tegra_cpu_reset_handler_enable(void)
    writel(reg, sb_ctrl);
    wmb();
    }
    +}
    +
    +static void __init tegra_cpu_reset_handler_enable(void)
    +{
    + void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE);
    + const u32 reset_address = TEGRA_IRAM_RESET_BASE +
    + tegra_cpu_reset_handler_offset;
    +
    + BUG_ON(is_enabled);
    + BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE);
    +
    + memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start,
    + tegra_cpu_reset_handler_size);
    +
    + tegra_cpu_reset_handler_set(reset_address);

    is_enabled = true;
    }
    --
    1.8.4


    \
     
     \ /
      Last update: 2013-10-04 19:01    [W:4.266 / U:0.380 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site