Messages in this thread | | | Date | Wed, 30 Oct 2013 11:48:44 +0000 | From | James Hogan <> | Subject | Re: perf events ring buffer memory barrier on powerpc |
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Hi Peter,
On 30/10/13 10:42, Peter Zijlstra wrote: > Subject: perf, tool: Add required memory barriers > > To match patch bf378d341e48 ("perf: Fix perf ring buffer memory > ordering") change userspace to also adhere to the ordering outlined. > > Most barrier implementations were gleaned from > arch/*/include/asm/barrier.h and with the exception of metag I'm fairly > sure they're correct.
Yeh...
Short answer: For Meta you're probably best off assuming CONFIG_METAG_SMP_WRITE_REORDERING=n and just using compiler barriers.
Long answer: The issue with write reordering between Meta's hardware threads beyond the cache is only with a particular SoC, and SMP is not used in production on it. It is possible to make the LINSYSEVENT_WR_COMBINE_FLUSH register writable to userspace (it's in a non-mappable region already) but even then the write to that register needs odd placement to be effective (before the shmem write rather than after - which isn't a place any existing barriers are guaranteed to be placed). I'm fairly confident we get away with it in the kernel, and userland normally just uses linked load/store instructions for atomicity which works fine.
Cheers James
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