Messages in this thread | | | Date | Mon, 28 Oct 2013 11:51:01 +0100 | From | Ingo Molnar <> | Subject | Re: [PATCH] X86: MM: Add PAT Type write-through in combination with mtrr |
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* Andreas Werner <wernerandy@gmx.de> wrote:
> On Mon, Oct 28, 2013 at 11:31:32AM +0100, Ingo Molnar wrote: > > > > * Borislav Petkov <bp@alien8.de> wrote: > > > > > On Mon, Oct 28, 2013 at 11:17:49AM +0100, Ingo Molnar wrote: > > > > > > > And regular write-back cacheable isn't sufficient because the > > > > CPU could do things like prefetch your range automatically? > > > > > > Yeah, he's doing a CLFLUSH anyway which basically makes it a > > > write-through... > > > > The CLFLUSH is done afterwards (making it a use-once thing), so WB > > might still be faster and would avoid the PAT headache ... > > > > Thanks, > > > > Ingo > What i do right now is: > 1. clflush the data range to read from my mmio device > 2. read the data. > On PCIe Tracer i see the pcie bursts. > > If i mark the region WB and call clflush my system will crash without > any message, it just stop working.
Yeah, I was wondering whether it's valid at all to mark IO memory as cacheable - with the lack of MESI transactions and all that ...
So it's apparently not valid and we've got to live with WT as the 'best' caching/bursting method for reads.
Thanks,
Ingo
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