Messages in this thread | | | Date | Tue, 15 Oct 2013 12:51:59 +0200 | From | Borislav Petkov <> | Subject | Re: [PATCH] x86: Run checksumming in parallel accross multiple alu's |
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On Tue, Oct 15, 2013 at 09:41:23AM +0200, Ingo Molnar wrote: > Most processors have hundreds of cachelines even in their L1 cache. > Thousands in the L2 cache, up to hundreds of thousands.
Also, I have this hazy memory of prefetch hints being harmful in some situations: https://lwn.net/Articles/444344/
-- Regards/Gruss, Boris.
Sent from a fat crate under my desk. Formatting is fine. --
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