Messages in this thread | | | Date | Tue, 29 Jan 2013 16:49:19 +0100 | From | Jiri Olsa <> | Subject | Re: [RFC/PATCH] perf x86: Add off-core event constraints for Sandy/IvyBridge micro architecture |
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On Mon, Jan 28, 2013 at 06:49:55PM +0100, Stephane Eranian wrote: > On Sun, Jan 27, 2013 at 6:33 PM, Jiri Olsa <jolsa@redhat.com> wrote: > > hi, > > I was looking at the offcore stuff and it looks like we might > > be missing some constraints for offcore response events on > > Sandy/IvyBridge. > > > > The table 18.8.5 (Off-core Response Performance Monitoring) > > in Intel SDM states PMC0 for 0xb7 and PMC3 for 0xbb, but > > there's no other explanation or related description. > > > > I can't say/ack if the counters looks bad or right with or > > without the patch so far.. so just curious ;-) > > > Those are artificial constraints which should not be there. > Remember that offcore_rsp uses an extra MSR which has > to be shared by all the counters on the PMU. So a way to > handle the sharing of that extra MSR is to impose an > artificial constraint on the event itself. If it can only run > on one counter, then you get the management of the > extra MSR for free, i.e., only one event gets it. > > In perf_events, we use a more sophisticated dynamic scheme > which does not use this artificial constraint. We can measure > the event multiple times and share the extra MSR if possible > (same value). Why multiple times you might ask? For instance, > with different priv levels. > > > Hope this helps.
nice, thanks a lot for explanation
jirka
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