Messages in this thread | | | Date | Mon, 28 Jan 2013 17:16:16 +0100 | From | Andi Kleen <> | Subject | Re: [PATCH 02/12] perf, x86: Basic Haswell PMU support v2 |
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> > +static struct event_constraint intel_hsw_event_constraints[] = > > +{ > > + FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ > > + FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ > > + FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ > > + INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ > > You're covering the entire event here, so comment should be: L1D_PEND_MISS.*
Ok.
> > > + INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ > > + INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ > > + EVENT_CONSTRAINT_END > > You are missing constraint on the following public events: > - CYCLE_ACTIVITY (0xa3)
AFAIK that's not a PEBS event.
> > > +}; > > + > > static u64 intel_pmu_event_map(int hw_event) > > { > > return intel_perfmon_event_map[hw_event]; > > @@ -2107,6 +2118,24 @@ __init int intel_pmu_init(void) > > break; > > > > > > + case 60: /* Haswell Client */ > > + case 70: > > + case 71: > > + memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, > > + sizeof(hw_cache_event_ids)); > > + > > + intel_pmu_lbr_init_nhm(); > > + > I suspect this one should be intel_pmu_lbr_init_snb(), otherwise > you inherit the broken filter workarounds.
Good point.
-Andi -- ak@linux.intel.com -- Speaking for myself only.
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