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    Subject[PATCH 08/18] perf, x86: Add Haswell specific transaction flag reporting
    Date
    From: Andi Kleen <ak@linux.intel.com>

    In the PEBS handler report the transaction flags using the new
    generic transaction flags facility. Most of them come from
    the "tsx_tuning" field in PEBSv2, but the abort code is derived
    from the RAX register reported in the PEBS record.

    Signed-off-by: Andi Kleen <ak@linux.intel.com>
    ---
    arch/x86/kernel/cpu/perf_event_intel_ds.c | 9 +++++++++
    1 files changed, 9 insertions(+), 0 deletions(-)

    diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
    index 3094caa..4b657c2 100644
    --- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
    +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
    @@ -677,6 +677,15 @@ static void __intel_pmu_pebs_event(struct perf_event *event,
    data.weight = ((struct pebs_record_v2 *)pebs)->nhm.lat;
    }

    + if ((event->attr.sample_type & PERF_SAMPLE_TRANSACTION) &&
    + x86_pmu.intel_cap.pebs_format >= 2) {
    + data.transaction =
    + ((struct pebs_record_v2 *)pebs)->tsx_tuning >> 32;
    + if ((data.transaction & PERF_SAMPLE_TXN_TRANSACTION) &&
    + (pebs->ax & 1))
    + data.transaction |= pebs->ax & 0xff000000;
    + }
    +
    if (has_branch_stack(event))
    data.br_stack = &cpuc->lbr_stack;

    --
    1.7.7.6


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