Messages in this thread Patch in this message | | | Date | Wed, 23 Jan 2013 09:21:50 +0000 | From | Andrew Murray <> | Subject | Re: [PATCH] PCI: Document PCIE BUS MPS parameters |
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On Wed, Jan 23, 2013 at 08:01:36AM +0000, Yijing Wang wrote: > Document PCIE BUS MPS parameters pcie_bus_tune_off, pcie_bus_safe, > pcie_bus_peer2peer, pcie_bus_perf into Documentation/kernel-parameters.txt. > These parameters were introduced by Jon Mason <mason@myri.com> at > commit 5f39e6705 and commit b03e7495a8. Document these into > kernel-parameters.txt help users to understand and use the parameters. > > Signed-off-by: Yijing Wang <wangyijing@huawei.com> > --- > Documentation/kernel-parameters.txt | 13 +++++++++++++ > 1 files changed, 13 insertions(+), 0 deletions(-) > > diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt > index 363e348..4dfa8d2 100644 > --- a/Documentation/kernel-parameters.txt > +++ b/Documentation/kernel-parameters.txt > @@ -2227,6 +2227,19 @@ bytes respectively. Such letter suffixes can also be entirely omitted. > This sorting is done to get a device > order compatible with older (<= 2.4) kernels. > nobfsort Don't sort PCI devices into breadth-first order. > + pcie_bus_tune_off [X86] Disable PCI-E MPS turning and using > + the BIOS configured MPS defaults. > + pcie_bus_safe [X86] Use the smallest common denominator MPS > + of the entire tree below a root complex for every device > + on that fabric. Can avoid inconsistent mps problem caused > + by hotplug. > + pcie_bus_perf [X86] Configure pcie device MPS to the largest > + allowable MPS based on its parent bus.Improve performance > + as much as possible. > + pcie_bus_peer2peer [X86] Make the system wide MPS the smallest > + possible value (128B).This configuration could prevent it > + from working by having the MPS on one root port different > + than the MPS on another. > cbiosize=nn[KMG] The fixed amount of bus space which is > reserved for the CardBus bridge's IO window. > The default value is 256 bytes. > I was searching for documentation on this the other day.
It's not just X86 that use these options, PowerPC and Tile also use them (grep for users of pcie_bus_configure_settings). I've also noticed a call to it from hotplug as well...
In addition these options also have an effect on MRRS - I've not figured out what effect they have, but you can look in drivers/pci/probe.c at the pcie_write_mrrs function.
Andrew Murray
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