Messages in this thread Patch in this message |  | | From | Andi Kleen <> | Subject | [PATCH 06/29] perf, x86: Support PERF_SAMPLE_ADDR on Haswell | Date | Thu, 17 Jan 2013 12:36:29 -0800 |
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From: Andi Kleen <ak@linux.intel.com>
Haswell supplies the address for every PEBS memory event, so always fill it in when the user requested it. It will be 0 when not useful (no memory access)
Signed-off-by: Andi Kleen <ak@linux.intel.com> --- arch/x86/kernel/cpu/perf_event_intel_ds.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c index 16d7c58..aa0f5fa 100644 --- a/arch/x86/kernel/cpu/perf_event_intel_ds.c +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c @@ -630,6 +630,10 @@ static void __intel_pmu_pebs_event(struct perf_event *event, else regs.flags &= ~PERF_EFLAGS_EXACT; + if ((event->attr.sample_type & PERF_SAMPLE_ADDR) && + x86_pmu.intel_cap.pebs_format >= 2) + data.addr = ((struct pebs_record_v2 *)pebs)->nhm.dla; + if (has_branch_stack(event)) data.br_stack = &cpuc->lbr_stack; -- 1.7.7.6
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