Messages in this thread |  | | From | Arnd Bergmann <> | Subject | Re: [PATCH 05/14] lib: Add I/O map cache implementation | Date | Thu, 10 Jan 2013 18:26:55 +0000 |
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On Thursday 10 January 2013, Thierry Reding wrote: > I don't understand how this would help. The encoding is like this: > > [27:24] extended register number > [23:16] bus number > [15:11] device number > [10: 8] function number > [ 7: 0] register number > > So it doesn't matter whether I use separate areas per bus or not. As > soon as the whole extended configuration space needs to be accessed a > whopping 28 bits (256 MiB) are required. > > What you propose would work if only regular configuration space is > supported. I'm not sure if that's an option.
I mean something like:
struct tegra_bus_private { ... void __iomem *config_space[16]; };
void tegra_scan_bus(struct pci_bus *bus) { int i; struct tegra_bus_private *priv = bus->dev->private;
for (i=0; i<16; i++) priv->config_space[i] = ioremap(config_space_phys + 65536 * bus->primary + i * SZ_1M, 65536);
... }
Arnd
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