| From | Arnd Bergmann <> | Subject | Re: [PATCH v3 05/31] arm64: MMU initialisation | Date | Fri, 7 Sep 2012 19:10:56 +0000 |
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On Friday 07 September 2012, Catalin Marinas wrote: > > This patch contains the initialisation of the memory blocks, MMU > attributes and the memory map. Only five memory types are defined: > Device nGnRnE (equivalent to Strongly Ordered), Device nGnRE (classic > Device memory), Device GRE, Normal Non-cacheable and Normal Cacheable. > Cache policies are supported via the memory attributes register > (MAIR_EL1) and only affect the Normal Cacheable mappings. > > This patch also adds the SPARSEMEM_VMEMMAP initialisation. > > Signed-off-by: Will Deacon <will.deacon@arm.com> > Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> > Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
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