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    Subject[ 130/135] drm/radeon: fix ordering in pll picking on dce4+
    3.2-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Alex Deucher <alexander.deucher@amd.com>

    commit ecd67955fd4c8e66e4df312098989d5fa7da624c upstream.

    No functional change, but re-order the cases so they
    evaluate properly due to the way the DCE macros work.

    Noticed by kallisti5 on IRC.

    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    [bwh: Backported to 3.2: drop the DCE6 case]
    Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
    ---
    drivers/gpu/drm/radeon/atombios_crtc.c | 8 ++++----
    1 file changed, 4 insertions(+), 4 deletions(-)

    --- a/drivers/gpu/drm/radeon/atombios_crtc.c
    +++ b/drivers/gpu/drm/radeon/atombios_crtc.c
    @@ -1468,10 +1468,10 @@ static int radeon_atom_pick_pll(struct d
    * crtc virtual pixel clock.
    */
    if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
    - if (ASIC_IS_DCE5(rdev))
    - return ATOM_DCPLL;
    - else if (rdev->clock.dp_extclk)
    + if (rdev->clock.dp_extclk)
    return ATOM_PPLL_INVALID;
    + else if (ASIC_IS_DCE5(rdev))
    + return ATOM_DCPLL;
    }
    }
    }



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