Messages in this thread | | | Date | Wed, 15 Aug 2012 11:42:16 +0300 | From | Jussi Kivilinna <> | Subject | Re: [PATCH] crypto: twofish - add x86_64/avx assembler implementation |
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Quoting Johannes Goetzfried <Johannes.Goetzfried@informatik.stud.uni-erlangen.de>:
> This patch adds a x86_64/avx assembler implementation of the Twofish block > cipher. The implementation processes eight blocks in parallel (two 4 block > chunk AVX operations). The table-lookups are done in general-purpose > registers. > For small blocksizes the 3way-parallel functions from the twofish-x86_64-3way > module are called. A good performance increase is provided for blocksizes > greater or equal to 128B. > > Patch has been tested with tcrypt and automated filesystem tests. > > Tcrypt benchmark results: > > Intel Core i5-2500 CPU (fam:6, model:42, step:7)
I started thinking about the performance on AMD Bulldozer. vmovq/vmovd/vpextr*/vpinsr* between FPU and general purpose registers on AMD CPU is alot slower (latencies from 8 to 12 cycles) than on Intel sandy-bridge (where instructions have latency of 1 to 2). See: http://www.agner.org/optimize/instruction_tables.pdf
It would be really good, if implementation could be tested on AMD CPU to determinate, if it causes performance regression. However I don't have access to machine with such CPU.
-Jussi
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