Messages in this thread | | | Date | Wed, 15 Aug 2012 10:30:50 +0800 | From | Fengguang Wu <> | Subject | Re: [PATCH] select GENERIC_ATOMIC64 for c6x/score/unicore32 archs |
| |
On Tue, Aug 14, 2012 at 12:22:49PM -0400, Mark Salter wrote: > On Tue, 2012-08-14 at 23:34 +0800, Fengguang Wu wrote: > > Sorry I have no compilers for build testing these changes, however the > > risk looks low and it's much better than to leave the arch broken, > > considering that Eric will do atomic64_t in the core fs/namespace.c > > code. > > > > CC: "Eric W. Biederman" <ebiederm@xmission.com> > > Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> > > --- > > > > Andrew: the arch maintainers have been CCed. Best is the maintainers > > respond, test and perhaps take the corresponding change. Let's see how > > this will work out.. > > > > > > arch/c6x/Kconfig | 1 + > > The c6x port also needs this: > > C6X: add L*_CACHE_SHIFT defines > > C6X currently lacks L*_CACHE_SHIFT defines which are used in a few > places in the generic kernel. This patch adds those missing defines. > > Signed-off-by: Mark Salter <msalter@redhat.com>
Thanks for the quick fix! git grep shows this:
lib/atomic64.c: addr >>= L1_CACHE_SHIFT;
So this patch is a prerequisite for the GENERIC_ATOMIC64 patch.
git grep also shows
arch/score/include/asm/cache.h:#define L1_CACHE_SHIFT 4
arch/unicore32/include/asm/cache.h:#define L1_CACHE_SHIFT (5)
So the other two archs are fine.
Thanks, Fengguang
| |