Messages in this thread | | | Date | Sun, 22 Jul 2012 19:43:40 +0800 | Subject | Re: [PATCH] perf/x86: Fix LLC-* and node-* events on Intel SandyBridge | From | "Yan, Zheng " <> |
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On Sat, Jul 21, 2012 at 12:48 AM, Peter Zijlstra <a.p.zijlstra@chello.nl> wrote: > On Tue, 2012-07-17 at 17:27 +0800, Yan, Zheng wrote: >> From: "Yan, Zheng" <zheng.z.yan@intel.com> >> >> LLC-* and node-* events require using the OFFCORE_RESPONSE events >> on SandyBridge, but the hw_cache_extra_regs is left uninitialized. >> This patch adds the missing extra register configure table for >> SandyBridge. > > Last time I tried this I couldn't get sane numbers out of it.. > > Does these encodings work, if so, do explain them. >
I have tested them and compared the results with Nehalme. I think they do work.
>> +#define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD) normal LLC reads + LLC reads generated by L2 prefetcher
>> +#define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO) normal RFO requests + RFO requests generated by L2 prefetcher
>> +#define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO) >> + >> +#define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \ >> + SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \ >> + SNB_HITM) SNB_SNP_ANY contains all snoop related bits, because we don't care the snoop information.
>> + >> +#define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY) >> +#define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY) >> + >> +#define SNB_L3_ACCESS SNB_RESP_ANY For LLC access, we don't care the supplier and snoop information.
>> +#define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM) If the supplier is DRAM, we consider it as LLC miss.
> Also: > >> +#define SNB_REMOTE (0xffULL << 23) > > I guess I can take this as an 'official' publication of this fact? > > (I knew those bits meant this, but I never got a response if I could > publish that information.) > See chapter 18.8.7 of Intel 64 SDM Volume 3 (Order Number 325384)
Regards Yan, Zheng
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