Messages in this thread | | | Date | Wed, 27 Jun 2012 09:13:20 -0300 | From | Mauro Carvalho Chehab <> | Subject | Re: [PATCH v3] edac: add support for Calxeda highbank memory controller |
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Em 26-06-2012 10:45, Rob Herring escreveu: > Mauro, > > On 06/13/2012 12:01 PM, Rob Herring wrote: >> From: Rob Herring <rob.herring@calxeda.com> >> >> Add support for memory controller on Calxeda Highbank platforms. Highbank >> platforms support a single 4GB mini-DIMM with 1-bit correction and 2-bit >> detection. >> >> Signed-off-by: Rob Herring <rob.herring@calxeda.com> >> --- >> v3: fix compile when EDAC_DEBUG is disabled > > Ping. linux-next is broken for highbank without this fix.
Patch replaced and merged on my trees (with a minor change, see below).
-next should likely get the fix tomorrow.
Thanks, Mauro.
>> .../devicetree/bindings/arm/calxeda/mem-ctrlr.txt | 17 ++ >> arch/arm/boot/dts/highbank.dts | 6 + >> drivers/edac/Kconfig | 9 +- >> drivers/edac/Makefile | 2 + >> drivers/edac/highbank_mc_edac.c | 264 ++++++++++++++++++++ >> 5 files changed, 297 insertions(+), 1 deletion(-) >> create mode 100644 Documentation/devicetree/bindings/arm/calxeda/mem-ctrlr.txt >> create mode 100644 drivers/edac/highbank_mc_edac.c >> >> diff --git a/Documentation/devicetree/bindings/arm/calxeda/mem-ctrlr.txt b/Documentation/devicetree/bindings/arm/calxeda/mem-ctrlr.txt >> new file mode 100644 >> index 0000000..5c74a0b >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/arm/calxeda/mem-ctrlr.txt >> @@ -0,0 +1,17 @@ >> +Calxeda DDR memory controller >> + >> +Properties: >> +- compatible : Should be "calxeda,hb-ddr-ctrl" >> +- reg : Address and size for DDR controller registers. >> +- interrupts : Interrupt for DDR controller. >> + >> +Example: >> + >> + memory-controller@fff00000 { >> + compatible = "calxeda,hb-ddr-ctrl"; >> + reg = <0xfff00000 0x1000>; >> + interrupts = <0 91 4>; >> + }; >> + >> + >> +
There are some extra blank likes at the end of this file. I removed them.
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