Messages in this thread | | | Date | Fri, 15 Jun 2012 11:49:11 +0100 | Subject | Re: [Xen-devel] [PATCH 1/2] x86/mm: remove arch-specific ptep_get_and_clear() function | From | Keir Fraser <> |
| |
On 15/06/2012 10:41, "David Vrabel" <david.vrabel@citrix.com> wrote:
> This reasoning is probably not correct. When a dirty bit must be > updated in a PTE the processor does a pagetable walk (possibly using any > cached page table structures). The AMD APM section 5.4.2 states: > > "The processor never sets the Accessed bit or the Dirty bit for a not > present page (P = 0)." > > and > > "If PTE[D] is cleared to 0, software can rely on the fact that the page > has not been written."
Writing of dirty and accessed bits is done as part of the page-table walk on TLB fill. A/D bits never have writeback caching semantics. It wouldn't be safe: e.g., on unmap, TLB flushes happen after ptes have been cleared (to avoid TLB-fill races), but that would mean that A/D updates could be lost even on non-explicit unmaps (e.g., page out) which is obviously bad.
> Thus this patch would /introduce/ a race where a dirty bit set would be > lost (rather than extending the window where this would happen). > > However (and this is a weaker argument), no sensible userspace > application should be accessing pages that are being unmapped or > remapped (since it is unpredictable whether they will fault) so perhaps > this additional unpredictable behaviour is acceptable?
If there's a big win to be had through batching, we're better off devising a hypercall method for capturing the atomic rmw operation as it stands, rather than subtly messing with semantics.
-- Keir
| |