Messages in this thread Patch in this message | | | From | xiong <> | Subject | [PATCH 06/10] atl1c: enlarge L1 response waiting timer | Date | Tue, 1 May 2012 09:38:54 +0800 |
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The hardware incorrectly process L0S/L1 entrance if the chipset/root response after specific/shorter timer and cause system hang. Enlarge the timeout value to avoid this issue.
Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> --- drivers/net/ethernet/atheros/atl1c/atl1c_hw.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h index 21a5bc1..17d935b 100644 --- a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h +++ b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h @@ -157,7 +157,7 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed); #define PM_CTRL_PM_REQ_TIMER_MASK 0xFUL #define PM_CTRL_PM_REQ_TIMER_SHIFT 20 /* pm_request_l1 time > @ * ->L0s not L1 */ -#define PM_CTRL_PM_REQ_TO_DEF 0xC +#define PM_CTRL_PM_REQ_TO_DEF 0xF #define PMCTRL_TXL1_AFTER_L0S BIT(19) /* l1dv2.0+ */ #define L1D_PMCTRL_L1_ENTRY_TM_MASK 7UL /* l1dv2.0+, 3bits */ #define L1D_PMCTRL_L1_ENTRY_TM_SHIFT 16 -- 1.7.7
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