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    Subject[ 40/68] drm/i915: gen7: implement rczunit workaround
    3.0-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Eugeni Dodonov <eugeni.dodonov@intel.com>

    commit eae66b50c760233fad526edf4a0d327be17a055d upstream.

    This is yet another workaround related to clock gating which we need on
    Ivy Bridge.

    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41353
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44610
    Tested-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
    Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
    Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
    Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    drivers/gpu/drm/i915/i915_reg.h | 1 +
    drivers/gpu/drm/i915/intel_display.c | 5 +++++
    2 files changed, 6 insertions(+)

    --- a/drivers/gpu/drm/i915/i915_reg.h
    +++ b/drivers/gpu/drm/i915/i915_reg.h
    @@ -3371,6 +3371,7 @@
    #define GT_FIFO_FREE_ENTRIES 0x120008

    #define GEN6_UCGCTL2 0x9404
    +# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
    # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
    # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)

    --- a/drivers/gpu/drm/i915/intel_display.c
    +++ b/drivers/gpu/drm/i915/intel_display.c
    @@ -7457,6 +7457,11 @@ static void ivybridge_init_clock_gating(
    I915_WRITE(WM2_LP_ILK, 0);
    I915_WRITE(WM1_LP_ILK, 0);

    + /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
    + * This implements the WaDisableRCZUnitClockGating workaround.
    + */
    + I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
    +
    I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);

    for_each_pipe(pipe)



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