Messages in this thread | | | Date | Thu, 29 Mar 2012 11:25:32 +0200 | From | Daniel Vetter <> | Subject | Re: [PATCH 5/7 v6] drm/i915/intel_i2c: use INDEX cycles for i2c read transactions |
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On Thu, Mar 29, 2012 at 04:37:18PM +0800, Daniel Kurtz wrote: > On Thu, Mar 29, 2012 at 2:52 AM, Chris Wilson <chris@chris-wilson.co.uk> wrote: > > On Thu, 29 Mar 2012 02:26:37 +0800, Daniel Kurtz <djkurtz@chromium.org> wrote: > >> It is very common for an i2c device to require a small 1 or 2 byte write > >> followed by a read. For example, when reading from an i2c EEPROM it is > >> common to write and address, offset or index followed by a reading some > >> values. > > > > Hmm, I have > > > > "gmbus1, bits 8-15: 8-bit GMBUS slave register > > This field is redundant and should not be used." > > > > Scary. :) > > Perhaps INDEX ops are only available on some chipsets? > Is this something you can double check?
I think index ops are available, the text sounds more like a hint to the programmer that for VCH devices you should use word reg index access (i.e. gmbus 5). We'll see when it blows up. -Daniel -- Daniel Vetter Mail: daniel@ffwll.ch Mobile: +41 (0)79 365 57 48 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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