Messages in this thread | | | Subject | Re: [PATCH 08/18] PCI, powerpc: Register busn_res for root buses | From | Benjamin Herrenschmidt <> | Date | Tue, 28 Feb 2012 19:54:32 +1100 |
| |
On Mon, 2012-02-27 at 22:36 -0700, Bjorn Helgaas wrote: > > There's a lot of powerpc code that does this: > > bus_range = of_get_property(pcictrl, "bus-range", &len); > hose->first_busno = bus_range[0]; > hose->last_busno = bus_range[1]; > > That *looks* like it is discovering the bus number aperture. Is it? > If it is, why are we using the largest bus number found by > pci_scan_child_bus() rather than "last_busno"?
We do that but we somewhat -also- rely on the core bumping it if it needs to make room :-)
As I said, we are swimming in dirty waters between reverse engineered stuff we don't know 100% and "designed" stuff.
I think we should have ways to more explicitely define what we want tho, ie whether hose->last_busno is just what happens to be the "current" bus number assigned by the firmware or the hard max. Maybe a pci flag ?
On the other hand some platforms (all the ppc4xx ones for example) set the flag to reassign all busses ... but have limit on bus numbers simply because they have a memory mapped only config space and we don't have enough address space to ioremap it all on 32-bit.
We need to fix them to use a fixmap entry to do atomic on-demand mapping of the config space and lift that restriction, but that isn't done yet.
So I think those patches will need really careful handling on our side.
Cheers, Ben.
| |