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Subject[PATCH 2/6 v7] clk, highbank: Prevent glitches in non-bypass reset mode
The highbank clock will glitch with the current code if the
clock rate is reset without relocking the PLL. Program the PLL
correctly to prevent glitches.

Signed-off-by: Mark Langsdorf <>
Signed-off-by: Rob Herring <>
Acked-by: Mike Turquette <>
Changes from v6
Changes from v5
Added Mike Turquette's ack.
Changes from v4
Changes from v3
Changelog text and patch name now correspond to the actual patch.
was clk, highbank: remove non-bypass reset mode.
Changes from v2
Changes from v1:
Removed erroneous reformating.

drivers/clk/clk-highbank.c | 2 ++
1 file changed, 2 insertions(+)

diff --git a/drivers/clk/clk-highbank.c b/drivers/clk/clk-highbank.c
index 52fecad..3a0b723 100644
--- a/drivers/clk/clk-highbank.c
+++ b/drivers/clk/clk-highbank.c
@@ -182,8 +182,10 @@ static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate,
reg |= HB_PLL_EXT_ENA;
} else {
+ writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
reg |= divq << HB_PLL_DIVQ_SHIFT;
+ writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
writel(reg, hbclk->reg);


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