Messages in this thread | | | Date | Wed, 19 Dec 2012 15:23:47 -0800 | From | "H. Peter Anvin" <> | Subject | Re: [tip:x86/microcode] x86/microcode_intel_early.c: Early update ucode on Intel's CPU |
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On 12/19/2012 02:55 PM, Jacob Shin wrote: > > Well, really the problem is with any memory hole above 4GB that is too > big to be covered by variable range MTRRs as UC. Because the kernel > use to just simply do init_memory_mapping for 4GB ~ top of memory, > any memory hole above 4GB are marked as WB in PATs. > > How is this handled in Intel architecture? If there are memory holes > that are too big to be covered by variable range MTRRs as UC, are > there other MTRR like CPU registers that the BIOS programs? >
Intel CPUs don't have the TOM augmentation to the MTRR mechanism, and so MTRRs need to explicitly enable caching of memory rather than the other way around.
-hpa
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