Messages in this thread | | | Date | Wed, 19 Dec 2012 17:21:34 -0600 | From | Jacob Shin <> | Subject | Re: [tip:x86/microcode] x86/microcode_intel_early.c: Early update ucode on Intel's CPU |
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On Thu, Dec 20, 2012 at 12:03:29AM +0100, Borislav Petkov wrote: > On Wed, Dec 19, 2012 at 04:59:41PM -0600, Jacob Shin wrote: > > I can check but right, they might be used up. But even if we had slots > > available, the memory range that needs to be covered is in large > > enough address and aligned in such a way that you cannot cover it with > > variable range MTRRs. > > Actually, if I'm not mistaken, you only need to cover the HT hole with > one MTRR - the rest remains WB. And in order the mask bits to work, we > could make it a little bigger - we waste some memory but that's nothing > in comparison to the MCE.
Actually all memory hole above 4GB and under TOM2 needs to be marked as UC, if the kernel just blanket calls init_memory_mapping from 4GB to top of memory.
Right we would be loosing memory, and I think depending on the alignment of the boundary and how many MTRRs you have avaiable to use, significant chunks of memory could be lost. I need to go refresh on how variable range MTRRs are programmed, it has been a while.
> > You might need to talk to hw guys about the feasibility of this deal > though. > > Thanks. > > -- > Regards/Gruss, > Boris. > > Sent from a fat crate under my desk. Formatting is fine. > -- >
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