Messages in this thread Patch in this message | | | From | Soren Brinkmann <> | Subject | [PATCH 2/7] arm: zynq: timer: Remove unnecessary register write | Date | Tue, 18 Dec 2012 16:16:34 -0800 |
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Acknowedging an interrupt requires to read the interrupt register only. The write was only required to work around a bug in the QEMU implementation of the TTC, which is fixed.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> --- @Peter: I took over your ACK, since it's the same change we applied to the Xilinx tree a couple of weeks ago. Let me know if this should be removed.
arch/arm/mach-zynq/timer.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c index 570491d..f1d224b 100644 --- a/arch/arm/mach-zynq/timer.c +++ b/arch/arm/mach-zynq/timer.c @@ -121,8 +121,7 @@ static irqreturn_t xttcps_clock_event_interrupt(int irq, void *dev_id) struct xttcps_timer *timer = &xttce->xttc; /* Acknowledge the interrupt and call event handler */ - __raw_writel(__raw_readl(timer->base_addr + XTTCPS_ISR_OFFSET), - timer->base_addr + XTTCPS_ISR_OFFSET); + __raw_readl(timer->base_addr + XTTCPS_ISR_OFFSET); xttce->ce.event_handler(&xttce->ce); -- 1.8.0.2
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