Messages in this thread - First message in thread
- "Philip, Avinash"
- "Philip, Avinash"
- "Philip, Avinash"
- "Philip, Avinash"
- "Philip, Avinash"
- "Philip, Avinash"
- "Philip, Avinash"
- "Philip, Avinash"
- "Philip, Avinash"
- "Bedia, Vaibhav"
- "Bedia, Vaibhav"
- "Bedia, Vaibhav"
- "Bedia, Vaibhav"
| | | From | "Philip, Avinash" <> | Subject | RE: [PATCH 6/8] pwm: pwm-tiehrpwm: Adding TBCLK gating support. | Date | Wed, 7 Nov 2012 15:20:30 +0000 |
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On Tue, Nov 06, 2012 at 12:16:13, Bedia, Vaibhav wrote: > On Mon, Nov 05, 2012 at 14:42:27, Philip, Avinash wrote: > [...] > > > + /* Some platforms require explicit tbclk gating */ > > + if (of_property_read_bool(pdev->dev.of_node, "tbclkgating")) { > > + pc->tbclk = clk_get(&pdev->dev, "tbclk"); > > + if (IS_ERR(pc->tbclk)) { > > + dev_err(&pdev->dev, "Could not get EHRPWM TBCLK\n"); > > + return PTR_ERR(pc->tbclk); > > + } > > + } > > + > > + /* Enable tbclk & leave */ > > + if (pc->tbclk) > > + clk_enable(pc->tbclk); > > + > > Here also why are you leaving this clock always running?
This is an additional clock gating for EHRPWM functional clock from control module. The enabling of this clock to pwm_enable & disabling to pwm_disable. I will correct it.
Thanks Avinash
> > Regards, > Vaibhav >
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