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SubjectRe: [PATCH v2 08/16] perf/x86: add memory profiling via PEBS Load Latency
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On Tue, Nov 6, 2012 at 7:50 PM, Andi Kleen <ak@linux.intel.com> wrote:
> On Tue, Nov 06, 2012 at 03:29:01PM +0100, Stephane Eranian wrote:
>> On Tue, Nov 6, 2012 at 2:31 PM, Andi Kleen <ak@linux.intel.com> wrote:
>> >> +EVENT_ATTR(cpu-cycles, CPU_CYCLES );
>> >> +EVENT_ATTR(instructions, INSTRUCTIONS );
>> >> +EVENT_ATTR(cache-references, CACHE_REFERENCES );
>> >> +EVENT_ATTR(cache-misses, CACHE_MISSES );
>> >> +EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS );
>> >> +EVENT_ATTR(branch-misses, BRANCH_MISSES );
>> >> +EVENT_ATTR(bus-cycles, BUS_CYCLES );
>> >> +EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND );
>> >> +EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND );
>> >> +EVENT_ATTR(ref-cycles, REF_CPU_CYCLES );
>> >
>> > The merge_events() approach from the Haswell patches should be far cleaner
>> >
>> And which patch in your HSW series implements this?
>
> [PATCH 27/32] perf, x86: Support CPU specific sysfs events
>
Will try using that one.
Thanks.


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