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    Subject[PATCH 2/8] ARM: am33xx: clk: Add optional clock for EHRPWM
    Date
    EHRPWM module requires explicit clock gating from control module.
    Hence add clock node in clock tree for EHRPWM modules.

    Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
    ---
    :100644 100644 17e3de5... 833260f... M arch/arm/mach-omap2/clock33xx_data.c
    :100644 100644 a89e825... c0e34e6... M arch/arm/mach-omap2/control.h
    arch/arm/mach-omap2/clock33xx_data.c | 37 ++++++++++++++++++++++++++++++++++
    arch/arm/mach-omap2/control.h | 8 +++++++
    2 files changed, 45 insertions(+), 0 deletions(-)

    diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c
    index 17e3de5..833260f 100644
    --- a/arch/arm/mach-omap2/clock33xx_data.c
    +++ b/arch/arm/mach-omap2/clock33xx_data.c
    @@ -995,6 +995,40 @@ static struct clk wdt1_fck = {
    };

    /*
    + * PWMSS Time based module clock node. This node is
    + * requred to enable clock gating for EHRPWM TBCLK.
    + */
    +static struct clk ehrpwm0_tbclk = {
    + .name = "ehrpwm0_tbclk",
    + .clkdm_name = "l4ls_clkdm",
    + .enable_reg = AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
    + .enable_bit = AM33XX_PWMSS0_TBCLKEN_SHIFT,
    + .ops = &clkops_omap2_dflt,
    + .parent = &l4ls_gclk,
    + .recalc = &followparent_recalc,
    +};
    +
    +static struct clk ehrpwm1_tbclk = {
    + .name = "ehrpwm1_tbclk",
    + .clkdm_name = "l4ls_clkdm",
    + .enable_reg = AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
    + .enable_bit = AM33XX_PWMSS1_TBCLKEN_SHIFT,
    + .ops = &clkops_omap2_dflt,
    + .parent = &l4ls_gclk,
    + .recalc = &followparent_recalc,
    +};
    +
    +static struct clk ehrpwm2_tbclk = {
    + .name = "ehrpwm2_tbclk",
    + .clkdm_name = "l4ls_clkdm",
    + .enable_reg = AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
    + .enable_bit = AM33XX_PWMSS2_TBCLKEN_SHIFT,
    + .ops = &clkops_omap2_dflt,
    + .parent = &l4ls_gclk,
    + .recalc = &followparent_recalc,
    +};
    +
    +/*
    * clkdev
    */
    static struct omap_clk am33xx_clks[] = {
    @@ -1074,6 +1108,9 @@ static struct omap_clk am33xx_clks[] = {
    CLK(NULL, "clkout2_ck", &clkout2_ck, CK_AM33XX),
    CLK(NULL, "timer_32k_ck", &clkdiv32k_ick, CK_AM33XX),
    CLK(NULL, "timer_sys_ck", &sys_clkin_ck, CK_AM33XX),
    + CLK(NULL, "ehrpwm0_tbclk", &ehrpwm0_tbclk, CK_AM33XX),
    + CLK(NULL, "ehrpwm1_tbclk", &ehrpwm1_tbclk, CK_AM33XX),
    + CLK(NULL, "ehrpwm2_tbclk", &ehrpwm2_tbclk, CK_AM33XX),
    };

    int __init am33xx_clk_init(void)
    diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
    index a89e825..c0e34e6 100644
    --- a/arch/arm/mach-omap2/control.h
    +++ b/arch/arm/mach-omap2/control.h
    @@ -357,6 +357,14 @@
    #define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH 0x2
    #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22)

    +/* AM33XX PWMSS Control register */
    +#define AM33XX_PWMSS_TBCLK_CLKCTRL 0x664
    +
    +/* AM33XX PWMSS Control bitfields */
    +#define AM33XX_PWMSS0_TBCLKEN_SHIFT 0
    +#define AM33XX_PWMSS1_TBCLKEN_SHIFT 1
    +#define AM33XX_PWMSS2_TBCLKEN_SHIFT 2
    +
    /* CONTROL OMAP STATUS register to identify OMAP3 features */
    #define OMAP3_CONTROL_OMAP_STATUS 0x044c

    --
    1.7.0.4


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